[xburst] Drop 2.6.32 patches

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22485 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 0 insertions, 519 deletions

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h
deleted file mode 100644
index 2ea90ca06..000000000
--- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- *  linux/include/asm-mips/mach-jz4740/regs.h
- *
- *  Ingenic's JZ4740 common include.
- *
- *  Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
- *
- *  Author: <yliu@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __JZ4740_REGS_H__
-#define __JZ4740_REGS_H__
-
-#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
-#define REG8(addr)	(addr)
-#define REG16(addr)	(addr)
-#define REG32(addr)	(addr)
-#else
-#define REG8(addr)	*((volatile unsigned char *)(addr))
-#define REG16(addr)	*((volatile unsigned short *)(addr))
-#define REG32(addr)	*((volatile unsigned int *)(addr))
-#endif
-
-/*
- * Define the module base addresses
- */
-#define	CPM_BASE	0xB0000000
-#define	INTC_BASE	0xB0001000
-#define	TCU_BASE	0xB0002000
-#define	WDT_BASE	0xB0002000
-#define	RTC_BASE	0xB0003000
-#define	GPIO_BASE	0xB0010000
-#define	AIC_BASE	0xB0020000
-#define	ICDC_BASE	0xB0020000
-#define	MSC_BASE	0xB0021000
-#define	UART0_BASE	0xB0030000
-#define	UART1_BASE	0xB0031000
-#define	I2C_BASE	0xB0042000
-#define	SSI_BASE	0xB0043000
-#define	SADC_BASE	0xB0070000
-#define	EMC_BASE	0xB3010000
-#define	DMAC_BASE	0xB3020000
-#define	UHC_BASE	0xB3030000
-#define	UDC_BASE	0xB3040000
-#define	LCD_BASE	0xB3050000
-#define	SLCD_BASE	0xB3050000
-#define	CIM_BASE	0xB3060000
-#define IPU_BASE	0xB3080000
-#define	ETH_BASE	0xB3100000
-
-/*************************************************************************
- * UART
- *************************************************************************/
-
-#define IRDA_BASE	UART0_BASE
-#define UART_BASE	UART0_BASE
-#define UART_OFF	0x1000
-
-/* Register Offset */
-#define OFF_RDR		(0x00)	/* R  8b H'xx */
-#define OFF_TDR		(0x00)	/* W  8b H'xx */
-#define OFF_DLLR	(0x00)	/* RW 8b H'00 */
-#define OFF_DLHR	(0x04)	/* RW 8b H'00 */
-#define OFF_IER		(0x04)	/* RW 8b H'00 */
-#define OFF_ISR		(0x08)	/* R  8b H'01 */
-#define OFF_FCR		(0x08)	/* W  8b H'00 */
-#define OFF_LCR		(0x0C)	/* RW 8b H'00 */
-#define OFF_MCR		(0x10)	/* RW 8b H'00 */
-#define OFF_LSR		(0x14)	/* R  8b H'00 */
-#define OFF_MSR		(0x18)	/* R  8b H'00 */
-#define OFF_SPR		(0x1C)	/* RW 8b H'00 */
-#define OFF_SIRCR	(0x20)	/* RW 8b H'00, UART0 */
-#define OFF_UMR		(0x24)	/* RW 8b H'00, UART M Register */
-#define OFF_UACR	(0x28)	/* RW 8b H'00, UART Add Cycle Register */
-
-/* Register Address */
-#define UART0_RDR	(UART0_BASE + OFF_RDR)
-#define UART0_TDR	(UART0_BASE + OFF_TDR)
-#define UART0_DLLR	(UART0_BASE + OFF_DLLR)
-#define UART0_DLHR	(UART0_BASE + OFF_DLHR)
-#define UART0_IER	(UART0_BASE + OFF_IER)
-#define UART0_ISR	(UART0_BASE + OFF_ISR)
-#define UART0_FCR	(UART0_BASE + OFF_FCR)
-#define UART0_LCR	(UART0_BASE + OFF_LCR)
-#define UART0_MCR	(UART0_BASE + OFF_MCR)
-#define UART0_LSR	(UART0_BASE + OFF_LSR)
-#define UART0_MSR	(UART0_BASE + OFF_MSR)
-#define UART0_SPR	(UART0_BASE + OFF_SPR)
-#define UART0_SIRCR	(UART0_BASE + OFF_SIRCR)
-#define UART0_UMR	(UART0_BASE + OFF_UMR)
-#define UART0_UACR	(UART0_BASE + OFF_UACR)
-
-/*
- * Define macros for UARTIER
- * UART Interrupt Enable Register
- */
-#define UARTIER_RIE	(1 << 0)	/* 0: receive fifo full interrupt disable */
-#define UARTIER_TIE	(1 << 1)	/* 0: transmit fifo empty interrupt disable */
-#define UARTIER_RLIE	(1 << 2)	/* 0: receive line status interrupt disable */
-#define UARTIER_MIE	(1 << 3)	/* 0: modem status interrupt disable */
-#define UARTIER_RTIE	(1 << 4)	/* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UARTISR
- * UART Interrupt Status Register
- */
-#define UARTISR_IP	(1 << 0)	/* 0: interrupt is pending  1: no interrupt */
-#define UARTISR_IID	(7 << 1)	/* Source of Interrupt */
-#define UARTISR_IID_MSI		(0 << 1)  /* Modem status interrupt */
-#define UARTISR_IID_THRI	(1 << 1)  /* Transmitter holding register empty */
-#define UARTISR_IID_RDI		(2 << 1)  /* Receiver data interrupt */
-#define UARTISR_IID_RLSI	(3 << 1)  /* Receiver line status interrupt */
-#define UARTISR_IID_RTO		(6 << 1)  /* Receive timeout */
-#define UARTISR_FFMS		(3 << 6)  /* FIFO mode select, set when UARTFCR.FE is set to 1 */
-#define UARTISR_FFMS_NO_FIFO	(0 << 6)
-#define UARTISR_FFMS_FIFO_MODE	(3 << 6)
-
-/*
- * Define macros for UARTFCR
- * UART FIFO Control Register
- */
-#define UARTFCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
-#define UARTFCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
-#define UARTFCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
-#define UARTFCR_DMS	(1 << 3)	/* 0: disable DMA mode */
-#define UARTFCR_UUE	(1 << 4)	/* 0: disable UART */
-#define UARTFCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
-#define UARTFCR_RTRG_1	(0 << 6)
-#define UARTFCR_RTRG_4	(1 << 6)
-#define UARTFCR_RTRG_8	(2 << 6)
-#define UARTFCR_RTRG_15	(3 << 6)
-
-/*
- * Define macros for UARTLCR
- * UART Line Control Register
- */
-#define UARTLCR_WLEN	(3 << 0)	/* word length */
-#define UARTLCR_WLEN_5	(0 << 0)
-#define UARTLCR_WLEN_6	(1 << 0)
-#define UARTLCR_WLEN_7	(2 << 0)
-#define UARTLCR_WLEN_8	(3 << 0)
-#define UARTLCR_STOP	(1 << 2)	/* 0: 1 stop bit when word length is 5,6,7,8
-					   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UARTLCR_STOP1	(0 << 2)
-#define UARTLCR_STOP2	(1 << 2)
-#define UARTLCR_PE	(1 << 3)	/* 0: parity disable */
-#define UARTLCR_PROE	(1 << 4)	/* 0: even parity  1: odd parity */
-#define UARTLCR_SPAR	(1 << 5)	/* 0: sticky parity disable */
-#define UARTLCR_SBRK	(1 << 6)	/* write 0 normal, write 1 send break */
-#define UARTLCR_DLAB	(1 << 7)	/* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */
-
-/*
- * Define macros for UARTLSR
- * UART Line Status Register
- */
-#define UARTLSR_DR	(1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */
-#define UARTLSR_ORER	(1 << 1)	/* 0: no overrun error */
-#define UARTLSR_PER	(1 << 2)	/* 0: no parity error */
-#define UARTLSR_FER	(1 << 3)	/* 0; no framing error */
-#define UARTLSR_BRK	(1 << 4)	/* 0: no break detected  1: receive a break signal */
-#define UARTLSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */
-#define UARTLSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */
-#define UARTLSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */
-
-/*
- * Define macros for UARTMCR
- * UART Modem Control Register
- */
-#define UARTMCR_RTS	(1 << 1)	/* 0: RTS_ output high, 1: RTS_ output low */
-#define UARTMCR_LOOP	(1 << 4)	/* 0: normal  1: loopback mode */
-#define UARTMCR_MCE	(1 << 7)	/* 0: modem function is disable */
-
-/*
- * Define macros for UARTMSR
- * UART Modem Status Register
- */
-#define UARTMSR_CCTS	(1 << 0)        /* 1: a change on CTS_ pin */
-#define UARTMSR_CTS	(1 << 4)	/* 0: CTS_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE	(1 << 0)  /* 0: transmitter is in UART mode  1: SIR mode */
-#define SIRCR_RSIRE	(1 << 1)  /* 0: receiver is in UART mode  1: SIR mode */
-#define SIRCR_TPWS	(1 << 2)  /* 0: transmit 0 pulse width is 3/16 of bit length
-					   1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TDPL	(1 << 3)  /* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RDPL	(1 << 4)  /* 0: decoder interprets positive pulse as 0 */
-
-
-/*************************************************************************
- * EMC (External Memory Controller)
- *************************************************************************/
-#define EMC_SMCR0	(EMC_BASE + 0x10)  /* Static Memory Control Register 0 */
-#define EMC_SMCR1	(EMC_BASE + 0x14)  /* Static Memory Control Register 1 */
-#define EMC_SMCR2	(EMC_BASE + 0x18)  /* Static Memory Control Register 2 */
-#define EMC_SMCR3	(EMC_BASE + 0x1c)  /* Static Memory Control Register 3 */
-#define EMC_SMCR4	(EMC_BASE + 0x20)  /* Static Memory Control Register 4 */
-#define EMC_SACR0	(EMC_BASE + 0x30)  /* Static Memory Bank 0 Addr Config Reg */
-#define EMC_SACR1	(EMC_BASE + 0x34)  /* Static Memory Bank 1 Addr Config Reg */
-#define EMC_SACR2	(EMC_BASE + 0x38)  /* Static Memory Bank 2 Addr Config Reg */
-#define EMC_SACR3	(EMC_BASE + 0x3c)  /* Static Memory Bank 3 Addr Config Reg */
-#define EMC_SACR4	(EMC_BASE + 0x40)  /* Static Memory Bank 4 Addr Config Reg */
-
-#define EMC_NFCSR	(EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
-#define EMC_NFECR	(EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
-#define EMC_NFECC	(EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
-#define EMC_NFPAR0	(EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
-#define EMC_NFPAR1	(EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
-#define EMC_NFPAR2	(EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
-#define EMC_NFINTS	(EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
-#define EMC_NFINTE	(EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
-#define EMC_NFERR0	(EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
-#define EMC_NFERR1	(EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
-#define EMC_NFERR2	(EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
-#define EMC_NFERR3	(EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
-
-#define EMC_DMCR	(EMC_BASE + 0x80)  /* DRAM Control Register */
-#define EMC_RTCSR	(EMC_BASE + 0x84)  /* Refresh Time Control/Status Register */
-#define EMC_RTCNT	(EMC_BASE + 0x88)  /* Refresh Timer Counter */
-#define EMC_RTCOR	(EMC_BASE + 0x8c)  /* Refresh Time Constant Register */
-#define EMC_DMAR0	(EMC_BASE + 0x90)  /* SDRAM Bank 0 Addr Config Register */
-#define EMC_SDMR0	(EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
-
-
-#define REG_EMC_SMCR0	REG32(EMC_SMCR0)
-#define REG_EMC_SMCR1	REG32(EMC_SMCR1)
-#define REG_EMC_SMCR2	REG32(EMC_SMCR2)
-#define REG_EMC_SMCR3	REG32(EMC_SMCR3)
-#define REG_EMC_SMCR4	REG32(EMC_SMCR4)
-#define REG_EMC_SACR0	REG32(EMC_SACR0)
-#define REG_EMC_SACR1	REG32(EMC_SACR1)
-#define REG_EMC_SACR2	REG32(EMC_SACR2)
-#define REG_EMC_SACR3	REG32(EMC_SACR3)
-#define REG_EMC_SACR4	REG32(EMC_SACR4)
-
-#define REG_EMC_NFCSR	REG32(EMC_NFCSR)
-#define REG_EMC_NFECR	REG32(EMC_NFECR)
-#define REG_EMC_NFECC	REG32(EMC_NFECC)
-#define REG_EMC_NFPAR0	REG32(EMC_NFPAR0)
-#define REG_EMC_NFPAR1	REG32(EMC_NFPAR1)
-#define REG_EMC_NFPAR2	REG32(EMC_NFPAR2)
-#define REG_EMC_NFINTS	REG32(EMC_NFINTS)
-#define REG_EMC_NFINTE	REG32(EMC_NFINTE)
-#define REG_EMC_NFERR0	REG32(EMC_NFERR0)
-#define REG_EMC_NFERR1	REG32(EMC_NFERR1)
-#define REG_EMC_NFERR2	REG32(EMC_NFERR2)
-#define REG_EMC_NFERR3	REG32(EMC_NFERR3)
-
-#define REG_EMC_DMCR	REG32(EMC_DMCR)
-#define REG_EMC_RTCSR	REG16(EMC_RTCSR)
-#define REG_EMC_RTCNT	REG16(EMC_RTCNT)
-#define REG_EMC_RTCOR	REG16(EMC_RTCOR)
-#define REG_EMC_DMAR0	REG32(EMC_DMAR0)
-
-/* Static Memory Control Register */
-#define EMC_SMCR_STRV_BIT	24
-#define EMC_SMCR_STRV_MASK	(0x0f << EMC_SMCR_STRV_BIT)
-#define EMC_SMCR_TAW_BIT	20
-#define EMC_SMCR_TAW_MASK	(0x0f << EMC_SMCR_TAW_BIT)
-#define EMC_SMCR_TBP_BIT	16
-#define EMC_SMCR_TBP_MASK	(0x0f << EMC_SMCR_TBP_BIT)
-#define EMC_SMCR_TAH_BIT	12
-#define EMC_SMCR_TAH_MASK	(0x07 << EMC_SMCR_TAH_BIT)
-#define EMC_SMCR_TAS_BIT	8
-#define EMC_SMCR_TAS_MASK	(0x07 << EMC_SMCR_TAS_BIT)
-#define EMC_SMCR_BW_BIT		6
-#define EMC_SMCR_BW_MASK	(0x03 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_8BIT	(0 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_16BIT	(1 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_32BIT	(2 << EMC_SMCR_BW_BIT)
-#define EMC_SMCR_BCM		(1 << 3)
-#define EMC_SMCR_BL_BIT		1
-#define EMC_SMCR_BL_MASK	(0x03 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_4		(0 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_8		(1 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_16	(2 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_32	(3 << EMC_SMCR_BL_BIT)
-#define EMC_SMCR_SMT		(1 << 0)
-
-/* Static Memory Bank Addr Config Reg */
-#define EMC_SACR_BASE_BIT	8
-#define EMC_SACR_BASE_MASK	(0xff << EMC_SACR_BASE_BIT)
-#define EMC_SACR_MASK_BIT	0
-#define EMC_SACR_MASK_MASK	(0xff << EMC_SACR_MASK_BIT)
-
-/* NAND Flash Control/Status Register */
-#define EMC_NFCSR_NFCE4		(1 << 7) /* NAND Flash Enable */
-#define EMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */
-#define EMC_NFCSR_NFCE3		(1 << 5)
-#define EMC_NFCSR_NFE3		(1 << 4)
-#define EMC_NFCSR_NFCE2		(1 << 3)
-#define EMC_NFCSR_NFE2		(1 << 2)
-#define EMC_NFCSR_NFCE1		(1 << 1)
-#define EMC_NFCSR_NFE1		(1 << 0)
-
-/* NAND Flash ECC Control Register */
-#define EMC_NFECR_PRDY		(1 << 4) /* Parity Ready */
-#define EMC_NFECR_RS_DECODING	(0 << 3) /* RS is in decoding phase */
-#define EMC_NFECR_RS_ENCODING	(1 << 3) /* RS is in encoding phase */
-#define EMC_NFECR_HAMMING	(0 << 2) /* Select HAMMING Correction Algorithm */
-#define EMC_NFECR_RS		(1 << 2) /* Select RS Correction Algorithm */
-#define EMC_NFECR_ERST		(1 << 1) /* ECC Reset */
-#define EMC_NFECR_ECCE		(1 << 0) /* ECC Enable */
-
-/* NAND Flash ECC Data Register */
-#define EMC_NFECC_ECC2_BIT	16
-#define EMC_NFECC_ECC2_MASK	(0xff << EMC_NFECC_ECC2_BIT)
-#define EMC_NFECC_ECC1_BIT	8
-#define EMC_NFECC_ECC1_MASK	(0xff << EMC_NFECC_ECC1_BIT)
-#define EMC_NFECC_ECC0_BIT	0
-#define EMC_NFECC_ECC0_MASK	(0xff << EMC_NFECC_ECC0_BIT)
-
-/* NAND Flash Interrupt Status Register */
-#define EMC_NFINTS_ERRCNT_BIT	29       /* Error Count */
-#define EMC_NFINTS_ERRCNT_MASK	(0x7 << EMC_NFINTS_ERRCNT_BIT)
-#define EMC_NFINTS_PADF		(1 << 4) /* Padding Finished */
-#define EMC_NFINTS_DECF		(1 << 3) /* Decoding Finished */
-#define EMC_NFINTS_ENCF		(1 << 2) /* Encoding Finished */
-#define EMC_NFINTS_UNCOR	(1 << 1) /* Uncorrectable Error Occurred */
-#define EMC_NFINTS_ERR		(1 << 0) /* Error Occurred */
-
-/* NAND Flash Interrupt Enable Register */
-#define EMC_NFINTE_PADFE	(1 << 4) /* Padding Finished Interrupt Enable */
-#define EMC_NFINTE_DECFE	(1 << 3) /* Decoding Finished Interrupt Enable */
-#define EMC_NFINTE_ENCFE	(1 << 2) /* Encoding Finished Interrupt Enable */
-#define EMC_NFINTE_UNCORE	(1 << 1) /* Uncorrectable Error Occurred Intr Enable */
-#define EMC_NFINTE_ERRE		(1 << 0) /* Error Occurred Interrupt */
-
-/* NAND Flash RS Error Report Register */
-#define EMC_NFERR_INDEX_BIT	16       /* Error Symbol Index */
-#define EMC_NFERR_INDEX_MASK	(0x1ff << EMC_NFERR_INDEX_BIT)
-#define EMC_NFERR_MASK_BIT	0        /* Error Symbol Value */
-#define EMC_NFERR_MASK_MASK	(0x1ff << EMC_NFERR_MASK_BIT)
-
-
-/* DRAM Control Register */
-#define EMC_DMCR_BW_BIT		31
-#define EMC_DMCR_BW		(1 << EMC_DMCR_BW_BIT)
-#define EMC_DMCR_CA_BIT		26
-#define EMC_DMCR_CA_MASK	(0x07 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_8		(0 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_9		(1 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_10	(2 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_11	(3 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_12	(4 << EMC_DMCR_CA_BIT)
-#define EMC_DMCR_RMODE		(1 << 25)
-#define EMC_DMCR_RFSH		(1 << 24)
-#define EMC_DMCR_MRSET		(1 << 23)
-#define EMC_DMCR_RA_BIT		20
-#define EMC_DMCR_RA_MASK	(0x03 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_11	(0 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_12	(1 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_13	(2 << EMC_DMCR_RA_BIT)
-#define EMC_DMCR_BA_BIT		19
-#define EMC_DMCR_BA		(1 << EMC_DMCR_BA_BIT)
-#define EMC_DMCR_PDM		(1 << 18)
-#define EMC_DMCR_EPIN		(1 << 17)
-#define EMC_DMCR_TRAS_BIT	13
-#define EMC_DMCR_TRAS_MASK	(0x07 << EMC_DMCR_TRAS_BIT)
-#define EMC_DMCR_RCD_BIT	11
-#define EMC_DMCR_RCD_MASK	(0x03 << EMC_DMCR_RCD_BIT)
-#define EMC_DMCR_TPC_BIT	8
-#define EMC_DMCR_TPC_MASK	(0x07 << EMC_DMCR_TPC_BIT)
-#define EMC_DMCR_TRWL_BIT	5
-#define EMC_DMCR_TRWL_MASK	(0x03 << EMC_DMCR_TRWL_BIT)
-#define EMC_DMCR_TRC_BIT	2
-#define EMC_DMCR_TRC_MASK	(0x07 << EMC_DMCR_TRC_BIT)
-#define EMC_DMCR_TCL_BIT	0
-#define EMC_DMCR_TCL_MASK	(0x03 << EMC_DMCR_TCL_BIT)
-
-/* Refresh Time Control/Status Register */
-#define EMC_RTCSR_CMF		(1 << 7)
-#define EMC_RTCSR_CKS_BIT	0
-#define EMC_RTCSR_CKS_MASK	(0x07 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_DISABLE	(0 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4	(1 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_16	(2 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_64	(3 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_256	(4 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_1024	(5 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_2048	(6 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4096	(7 << EMC_RTCSR_CKS_BIT)
-
-/* SDRAM Bank Address Configuration Register */
-#define EMC_DMAR_BASE_BIT	8
-#define EMC_DMAR_BASE_MASK	(0xff << EMC_DMAR_BASE_BIT)
-#define EMC_DMAR_MASK_BIT	0
-#define EMC_DMAR_MASK_MASK	(0xff << EMC_DMAR_MASK_BIT)
-
-/* Mode Register of SDRAM bank 0 */
-#define EMC_SDMR_BM		(1 << 9) /* Write Burst Mode */
-#define EMC_SDMR_OM_BIT		7        /* Operating Mode */
-#define EMC_SDMR_OM_MASK	(3 << EMC_SDMR_OM_BIT)
-  #define EMC_SDMR_OM_NORMAL	(0 << EMC_SDMR_OM_BIT)
-#define EMC_SDMR_CAS_BIT	4        /* CAS Latency */
-#define EMC_SDMR_CAS_MASK	(7 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_1	(1 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_2	(2 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_3	(3 << EMC_SDMR_CAS_BIT)
-#define EMC_SDMR_BT_BIT		3        /* Burst Type */
-#define EMC_SDMR_BT_MASK	(1 << EMC_SDMR_BT_BIT)
-  #define EMC_SDMR_BT_SEQ	(0 << EMC_SDMR_BT_BIT) /* Sequential */
-  #define EMC_SDMR_BT_INT	(1 << EMC_SDMR_BT_BIT) /* Interleave */
-#define EMC_SDMR_BL_BIT		0        /* Burst Length */
-#define EMC_SDMR_BL_MASK	(7 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_1		(0 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_2		(1 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_4		(2 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_8		(3 << EMC_SDMR_BL_BIT)
-
-#define EMC_SDMR_CAS2_16BIT \
-  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS2_32BIT \
-  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-#define EMC_SDMR_CAS3_16BIT \
-  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS3_32BIT \
-  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-
-/*************************************************************************
- * WDT (WatchDog Timer)
- *************************************************************************/
-#define WDT_TDR		(WDT_BASE + 0x00)
-#define WDT_TCER	(WDT_BASE + 0x04)
-#define WDT_TCNT	(WDT_BASE + 0x08)
-#define WDT_TCSR	(WDT_BASE + 0x0C)
-
-#define REG_WDT_TDR	REG16(WDT_TDR)
-#define REG_WDT_TCER	REG8(WDT_TCER)
-#define REG_WDT_TCNT	REG16(WDT_TCNT)
-#define REG_WDT_TCSR	REG16(WDT_TCSR)
-
-// Register definition
-#define WDT_TCSR_PRESCALE_BIT	3
-#define WDT_TCSR_PRESCALE_MASK	(0x7 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1	(0x0 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE4	(0x1 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE16	(0x2 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE64	(0x3 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE256	(0x4 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1024	(0x5 << WDT_TCSR_PRESCALE_BIT)
-#define WDT_TCSR_EXT_EN		(1 << 2)
-#define WDT_TCSR_RTC_EN		(1 << 1)
-#define WDT_TCSR_PCK_EN		(1 << 0)
-
-#define WDT_TCER_TCEN		(1 << 0)
-
-/*************************************************************************
- * RTC
- *************************************************************************/
-#define RTC_RCR		(RTC_BASE + 0x00) /* RTC Control Register */
-#define RTC_RSR		(RTC_BASE + 0x04) /* RTC Second Register */
-#define RTC_RSAR	(RTC_BASE + 0x08) /* RTC Second Alarm Register */
-#define RTC_RGR		(RTC_BASE + 0x0c) /* RTC Regulator Register */
-
-#define RTC_HCR		(RTC_BASE + 0x20) /* Hibernate Control Register */
-#define RTC_HWFCR	(RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
-#define RTC_HRCR	(RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
-#define RTC_HWCR	(RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
-#define RTC_HWRSR	(RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
-#define RTC_HSPR	(RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
-
-#define REG_RTC_RCR	REG32(RTC_RCR)
-#define REG_RTC_RSR	REG32(RTC_RSR)
-#define REG_RTC_RSAR	REG32(RTC_RSAR)
-#define REG_RTC_RGR	REG32(RTC_RGR)
-#define REG_RTC_HCR	REG32(RTC_HCR)
-#define REG_RTC_HWFCR	REG32(RTC_HWFCR)
-#define REG_RTC_HRCR	REG32(RTC_HRCR)
-#define REG_RTC_HWCR	REG32(RTC_HWCR)
-#define REG_RTC_HWRSR	REG32(RTC_HWRSR)
-#define REG_RTC_HSPR	REG32(RTC_HSPR)
-
-/* RTC Control Register */
-#define RTC_RCR_WRDY_BIT 7
-#define RTC_RCR_WRDY	(1 << 7)  /* Write Ready Flag */
-#define RTC_RCR_1HZ_BIT	6
-#define RTC_RCR_1HZ	(1 << RTC_RCR_1HZ_BIT)  /* 1Hz Flag */
-#define RTC_RCR_1HZIE	(1 << 5)  /* 1Hz Interrupt Enable */
-#define RTC_RCR_AF_BIT	4
-#define RTC_RCR_AF	(1 << RTC_RCR_AF_BIT)  /* Alarm Flag */
-#define RTC_RCR_AIE	(1 << 3)  /* Alarm Interrupt Enable */
-#define RTC_RCR_AE	(1 << 2)  /* Alarm Enable */
-#define RTC_RCR_RTCE	(1 << 0)  /* RTC Enable */
-
-/* RTC Regulator Register */
-#define RTC_RGR_LOCK		(1 << 31) /* Lock Bit */
-#define RTC_RGR_ADJC_BIT	16
-#define RTC_RGR_ADJC_MASK	(0x3ff << RTC_RGR_ADJC_BIT)
-#define RTC_RGR_NC1HZ_BIT	0
-#define RTC_RGR_NC1HZ_MASK	(0xffff << RTC_RGR_NC1HZ_BIT)
-
-/* Hibernate Control Register */
-#define RTC_HCR_PD		(1 << 0)  /* Power Down */
-
-/* Hibernate Wakeup Filter Counter Register */
-#define RTC_HWFCR_BIT		5
-#define RTC_HWFCR_MASK		(0x7ff << RTC_HWFCR_BIT)
-
-/* Hibernate Reset Counter Register */
-#define RTC_HRCR_BIT		5
-#define RTC_HRCR_MASK		(0x7f << RTC_HRCR_BIT)
-
-/* Hibernate Wakeup Control Register */
-#define RTC_HWCR_EALM		(1 << 0)  /* RTC alarm wakeup enable */
-
-/* Hibernate Wakeup Status Register */
-#define RTC_HWRSR_HR		(1 << 5)  /* Hibernate reset */
-#define RTC_HWRSR_PPR		(1 << 4)  /* PPR reset */
-#define RTC_HWRSR_PIN		(1 << 1)  /* Wakeup pin status bit */
-#define RTC_HWRSR_ALM		(1 << 0)  /* RTC alarm status bit */
-
-#endif /* __JZ4740_REGS_H__ */