diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ar7/config-2.6.35 | 160 | ||||
| -rw-r--r-- | target/linux/ar7/files/drivers/char/ar7_gpio.c (renamed from target/linux/ar7/files-2.6.32/drivers/char/ar7_gpio.c) | 0 | ||||
| -rw-r--r-- | target/linux/ar7/files/drivers/mtd/titanpart.c (renamed from target/linux/ar7/files-2.6.32/drivers/mtd/titanpart.c) | 0 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/110-flash.patch | 11 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/120-gpio_chrdev.patch | 28 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/500-serial_kludge.patch | 28 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/920-ar7part.patch | 55 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/930-titan-platform.patch | 781 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/940-cpmac-titan.patch | 108 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/970-remove_fixed_phy.patch | 78 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/971-cpmac_cleanup.patch | 69 | ||||
| -rw-r--r-- | target/linux/ar7/patches-2.6.35/972-cpmac_multi_probe.patch | 65 |
12 files changed, 1383 insertions, 0 deletions
diff --git a/target/linux/ar7/config-2.6.35 b/target/linux/ar7/config-2.6.35 new file mode 100644 index 000000000..7217c246d --- /dev/null +++ b/target/linux/ar7/config-2.6.35 @@ -0,0 +1,160 @@ +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_ADM6996_PHY=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_AR7=y +CONFIG_AR7_GPIO=y +CONFIG_AR7_WDT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +CONFIG_BITREVERSE=y +CONFIG_BOOT_ELF32=y +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +CONFIG_CEVT_R4K=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CPMAC=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_MIPSR1=y +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_VR41XX is not set +CONFIG_CSRC_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DECOMPRESS_LZMA=y +# CONFIG_DM9000 is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +# CONFIG_FSNOTIFY is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_GPIOLIB=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HW_RANDOM=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IP17XX_PHY=y +CONFIG_IRQ_CPU=y +CONFIG_KALLSYMS=y +CONFIG_LEDS_GPIO=y +# CONFIG_LOONGSON_MC146818 is not set +CONFIG_LOONGSON_UART_BASE=y +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MIKROTIK_RB532 is not set +CONFIG_MIPS=y +# CONFIG_MIPS_COBALT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_SIM is not set +CONFIG_MTD_AR7_PARTS=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MVSWITCH_PHY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NO_EXCEPT_FILL=y +# CONFIG_NO_IOPORT is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PHYLIB=y +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_POWERTV is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_SCSI_DMA is not set +CONFIG_SCSI_MOD=y +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y +# CONFIG_TINY_RCU is not set +CONFIG_TRAD_SIGNALS=y +CONFIG_TREE_RCU=y +CONFIG_VLYNQ=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ar7/files-2.6.32/drivers/char/ar7_gpio.c b/target/linux/ar7/files/drivers/char/ar7_gpio.c index 6b38bbd89..6b38bbd89 100644 --- a/target/linux/ar7/files-2.6.32/drivers/char/ar7_gpio.c +++ b/target/linux/ar7/files/drivers/char/ar7_gpio.c diff --git a/target/linux/ar7/files-2.6.32/drivers/mtd/titanpart.c b/target/linux/ar7/files/drivers/mtd/titanpart.c index 74f8251a2..74f8251a2 100644 --- a/target/linux/ar7/files-2.6.32/drivers/mtd/titanpart.c +++ b/target/linux/ar7/files/drivers/mtd/titanpart.c diff --git a/target/linux/ar7/patches-2.6.35/110-flash.patch b/target/linux/ar7/patches-2.6.35/110-flash.patch new file mode 100644 index 000000000..0d14c978e --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/110-flash.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/maps/physmap.c ++++ b/drivers/mtd/maps/physmap.c +@@ -79,7 +79,7 @@ static const char *rom_probe_types[] = { + "map_rom", + NULL }; + #ifdef CONFIG_MTD_PARTITIONS +-static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; ++static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "ar7part", NULL }; + #endif + + static int physmap_flash_probe(struct platform_device *dev) diff --git a/target/linux/ar7/patches-2.6.35/120-gpio_chrdev.patch b/target/linux/ar7/patches-2.6.35/120-gpio_chrdev.patch new file mode 100644 index 000000000..c02cfb9d4 --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/120-gpio_chrdev.patch @@ -0,0 +1,28 @@ +--- a/drivers/char/Kconfig ++++ b/drivers/char/Kconfig +@@ -990,6 +990,15 @@ config MWAVE + To compile this driver as a module, choose M here: the + module will be called mwave. + ++config AR7_GPIO ++ tristate "TI AR7 GPIO Support" ++ depends on AR7 ++ help ++ Give userspace access to the GPIO pins on the Texas Instruments AR7 ++ processors. ++ ++ If compiled as a module, it will be called ar7_gpio. ++ + config SCx200_GPIO + tristate "NatSemi SCx200 GPIO Support" + depends on SCx200 +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -92,6 +92,7 @@ obj-$(CONFIG_HW_RANDOM) += hw_random/ + obj-$(CONFIG_PPDEV) += ppdev.o + obj-$(CONFIG_NWBUTTON) += nwbutton.o + obj-$(CONFIG_NWFLASH) += nwflash.o ++obj-$(CONFIG_AR7_GPIO) += ar7_gpio.o + obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o + obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o + obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o diff --git a/target/linux/ar7/patches-2.6.35/500-serial_kludge.patch b/target/linux/ar7/patches-2.6.35/500-serial_kludge.patch new file mode 100644 index 000000000..bba8c99ad --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/500-serial_kludge.patch @@ -0,0 +1,28 @@ +--- a/drivers/serial/8250.c ++++ b/drivers/serial/8250.c +@@ -300,6 +300,13 @@ static const struct serial8250_config ua + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, + .flags = UART_CAP_FIFO | UART_CAP_AFE, + }, ++ [PORT_AR7] = { ++ .name = "TI-AR7", ++ .fifo_size = 16, ++ .tx_loadsz = 16, ++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, ++ .flags = UART_CAP_FIFO | UART_CAP_AFE, ++ }, + }; + + #if defined (CONFIG_SERIAL_8250_AU1X00) +@@ -2746,7 +2753,11 @@ static void serial8250_console_putchar(s + { + struct uart_8250_port *up = (struct uart_8250_port *)port; + ++#ifdef CONFIG_AR7 ++ wait_for_xmitr(up, BOTH_EMPTY); ++#else + wait_for_xmitr(up, UART_LSR_THRE); ++#endif + serial_out(up, UART_TX, ch); + } + diff --git a/target/linux/ar7/patches-2.6.35/920-ar7part.patch b/target/linux/ar7/patches-2.6.35/920-ar7part.patch new file mode 100644 index 000000000..984663547 --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/920-ar7part.patch @@ -0,0 +1,55 @@ +--- a/drivers/mtd/ar7part.c ++++ b/drivers/mtd/ar7part.c +@@ -27,12 +27,14 @@ + #include <linux/mtd/partitions.h> + #include <linux/bootmem.h> + #include <linux/magic.h> ++#include <asm/mach-ar7/prom.h> + + #define AR7_PARTS 4 + #define ROOT_OFFSET 0xe0000 + + #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42) + #define LOADER_MAGIC2 le32_to_cpu(0xfeed1281) ++#define LOADER_MAGIC3 le32_to_cpu(0x434d4d4c) + + #ifndef SQUASHFS_MAGIC + #define SQUASHFS_MAGIC 0x73717368 +@@ -44,6 +46,10 @@ struct ar7_bin_rec { + unsigned int address; + }; + ++int create_titan_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ unsigned long origin); ++ + static int create_mtd_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + unsigned long origin) +@@ -57,6 +63,16 @@ static int create_mtd_partitions(struct + int retries = 10; + struct mtd_partition *ar7_parts; + ++ const char *prod_id ; ++ prod_id = prom_getenv("ProductID"); ++ if(prod_id && ++ (strcmp(prod_id, "CYWL")==0 || ++ strcmp(prod_id, "CYWM")==0 || ++ strcmp(prod_id, "CYLM")==0 || ++ strcmp(prod_id, "CYLL")==0)){ ++ return create_titan_partitions(master, pparts, origin); ++ } ++ + ar7_parts = kzalloc(sizeof(*ar7_parts) * AR7_PARTS, GFP_KERNEL); + if (!ar7_parts) + return -ENOMEM; +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redbo + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o + obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o ++obj-$(CONFIG_MTD_AR7_PARTS) += titanpart.o + obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o + diff --git a/target/linux/ar7/patches-2.6.35/930-titan-platform.patch b/target/linux/ar7/patches-2.6.35/930-titan-platform.patch new file mode 100644 index 000000000..0afe14fbe --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/930-titan-platform.patch @@ -0,0 +1,781 @@ +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -154,6 +154,60 @@ static struct resource vlynq_high_res[] + }, + }; + ++static struct resource vlynq_low_res_titan[] = { ++ { ++ .name = "regs", ++ .flags = IORESOURCE_MEM, ++ .start = TITAN_REGS_VLYNQ0, ++ .end = TITAN_REGS_VLYNQ0 + 0xff, ++ }, ++ { ++ .name = "irq", ++ .flags = IORESOURCE_IRQ, ++ .start = 33, ++ .end = 33, ++ }, ++ { ++ .name = "mem", ++ .flags = IORESOURCE_MEM, ++ .start = 0x0c000000, ++ .end = 0x0fffffff, ++ }, ++ { ++ .name = "devirq", ++ .flags = IORESOURCE_IRQ, ++ .start = 80, ++ .end = 111, ++ }, ++}; ++ ++static struct resource vlynq_high_res_titan[] = { ++ { ++ .name = "regs", ++ .flags = IORESOURCE_MEM, ++ .start = TITAN_REGS_VLYNQ1, ++ .end = TITAN_REGS_VLYNQ1 + 0xff, ++ }, ++ { ++ .name = "irq", ++ .flags = IORESOURCE_IRQ, ++ .start = 34, ++ .end = 34, ++ }, ++ { ++ .name = "mem", ++ .flags = IORESOURCE_MEM, ++ .start = 0x40000000, ++ .end = 0x43ffffff, ++ }, ++ { ++ .name = "devirq", ++ .flags = IORESOURCE_IRQ, ++ .start = 112, ++ .end = 143, ++ }, ++}; ++ + static struct plat_vlynq_data vlynq_low_data = { + .ops = { + .on = vlynq_on, +@@ -192,6 +246,44 @@ static struct platform_device vlynq_high + .num_resources = ARRAY_SIZE(vlynq_high_res), + }; + ++static struct plat_vlynq_data vlynq_low_data_titan = { ++ .ops = { ++ .on = vlynq_on, ++ .off = vlynq_off, ++ }, ++ .reset_bit = 15, ++ .gpio_bit = 14, ++}; ++ ++static struct plat_vlynq_data vlynq_high_data_titan = { ++ .ops = { ++ .on = vlynq_on, ++ .off = vlynq_off, ++ }, ++ .reset_bit = 16, ++ .gpio_bit = 7, ++}; ++ ++static struct platform_device vlynq_low_titan = { ++ .id = 0, ++ .name = "vlynq", ++ .dev = { ++ .platform_data = &vlynq_low_data_titan, ++ }, ++ .resource = vlynq_low_res_titan, ++ .num_resources = ARRAY_SIZE(vlynq_low_res_titan), ++}; ++ ++static struct platform_device vlynq_high_titan = { ++ .id = 1, ++ .name = "vlynq", ++ .dev = { ++ .platform_data = &vlynq_high_data_titan, ++ }, ++ .resource = vlynq_high_res_titan, ++ .num_resources = ARRAY_SIZE(vlynq_high_res_titan), ++}; ++ + /***************************************************************************** + * Flash + ****************************************************************************/ +@@ -248,6 +340,36 @@ static struct resource cpmac_high_res[] + }, + }; + ++static struct resource cpmac_low_res_titan[] = { ++ { ++ .name = "regs", ++ .flags = IORESOURCE_MEM, ++ .start = TITAN_REGS_MAC0, ++ .end = TITAN_REGS_MAC0 + 0x7ff, ++ }, ++ { ++ .name = "irq", ++ .flags = IORESOURCE_IRQ, ++ .start = 27, ++ .end = 27, ++ }, ++}; ++ ++static struct resource cpmac_high_res_titan[] = { ++ { ++ .name = "regs", ++ .flags = IORESOURCE_MEM, ++ .start = TITAN_REGS_MAC1, ++ .end = TITAN_REGS_MAC1 + 0x7ff, ++ }, ++ { ++ .name = "irq", ++ .flags = IORESOURCE_IRQ, ++ .start = 41, ++ .end = 41, ++ }, ++}; ++ + static struct fixed_phy_status fixed_phy_status __initdata = { + .link = 1, + .speed = 100, +@@ -292,6 +414,42 @@ static struct platform_device cpmac_high + .num_resources = ARRAY_SIZE(cpmac_high_res), + }; + ++static struct plat_cpmac_data cpmac_low_data_titan = { ++ .reset_bit = 17, ++ .power_bit = 20, ++ .phy_mask = 0x40000000, ++}; ++ ++static struct plat_cpmac_data cpmac_high_data_titan = { ++ .reset_bit = 21, ++ .power_bit = 22, ++ .phy_mask = 0x80000000, ++}; ++ ++static struct platform_device cpmac_low_titan = { ++ .id = 0, ++ .name = "cpmac", ++ .dev = { ++ .dma_mask = &cpmac_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ .platform_data = &cpmac_low_data_titan, ++ }, ++ .resource = cpmac_low_res_titan, ++ .num_resources = ARRAY_SIZE(cpmac_low_res_titan), ++}; ++ ++static struct platform_device cpmac_high_titan = { ++ .id = 1, ++ .name = "cpmac", ++ .dev = { ++ .dma_mask = &cpmac_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ .platform_data = &cpmac_high_data_titan, ++ }, ++ .resource = cpmac_high_res_titan, ++ .num_resources = ARRAY_SIZE(cpmac_high_res_titan), ++}; ++ + static inline unsigned char char2hex(char h) + { + switch (h) { +@@ -369,6 +527,11 @@ static struct gpio_led default_leds[] = + }, + }; + ++static struct gpio_led titan_leds[] = { ++ { .name = "status", .gpio = 8, .active_low = 1, }, ++ { .name = "wifi", .gpio = 13, .active_low = 1, }, ++}; ++ + static struct gpio_led dsl502t_leds[] = { + { + .name = "status", +@@ -507,6 +670,9 @@ static void __init detect_leds(void) + } else if (strstr(prid, "DG834")) { + ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds); + ar7_led_data.leds = dg834g_leds; ++ } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { ++ ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); ++ ar7_led_data.leds = titan_leds; + } + } + +@@ -586,14 +752,18 @@ static int __init ar7_register_devices(v + if (res) + pr_warning("unable to register physmap-flash: %d\n", res); + +- ar7_device_disable(vlynq_low_data.reset_bit); +- res = platform_device_register(&vlynq_low); ++ ar7_device_disable(ar7_is_titan() ? vlynq_low_data_titan.reset_bit : ++ vlynq_low_data.reset_bit); ++ res = platform_device_register(ar7_is_titan() ? &vlynq_low_titan : ++ &vlynq_low); + if (res) + pr_warning("unable to register vlynq-low: %d\n", res); + + if (ar7_has_high_vlynq()) { +- ar7_device_disable(vlynq_high_data.reset_bit); +- res = platform_device_register(&vlynq_high); ++ ar7_device_disable(ar7_is_titan() ? vlynq_high_data_titan.reset_bit : ++ vlynq_high_data.reset_bit); ++ res = platform_device_register(ar7_is_titan() ? &vlynq_high_titan : ++ &vlynq_high); + if (res) + pr_warning("unable to register vlynq-high: %d\n", res); + } +--- a/arch/mips/ar7/gpio.c ++++ b/arch/mips/ar7/gpio.c +@@ -37,6 +37,16 @@ static int ar7_gpio_get_value(struct gpi + return readl(gpio_in) & (1 << gpio); + } + ++static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ void __iomem *gpio_in0 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0); ++ void __iomem *gpio_in1 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1); ++ ++ return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f)); ++} ++ + static void ar7_gpio_set_value(struct gpio_chip *chip, + unsigned gpio, int value) + { +@@ -51,6 +61,21 @@ static void ar7_gpio_set_value(struct gp + writel(tmp, gpio_out); + } + ++static void titan_gpio_set_value(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ void __iomem *gpio_out0 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0); ++ void __iomem *gpio_out1 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1); ++ unsigned tmp; ++ ++ tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f)); ++ if (value) ++ tmp |= 1 << (gpio & 0x1f); ++ writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0); ++} ++ + static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) + { + struct ar7_gpio_chip *gpch = +@@ -62,6 +87,21 @@ static int ar7_gpio_direction_input(stru + return 0; + } + ++static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) ++{ ++ void __iomem *gpio_dir0 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0); ++ void __iomem *gpio_dir1 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1); ++ ++ if (gpio >= TITAN_GPIO_MAX) ++ return -EINVAL; ++ ++ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), ++ gpio >> 5 ? gpio_dir1 : gpio_dir0); ++ return 0; ++} ++ + static int ar7_gpio_direction_output(struct gpio_chip *chip, + unsigned gpio, int value) + { +@@ -75,6 +115,24 @@ static int ar7_gpio_direction_output(str + return 0; + } + ++static int titan_gpio_direction_output(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ void __iomem *gpio_dir0 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0); ++ void __iomem *gpio_dir1 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1); ++ ++ if (gpio >= TITAN_GPIO_MAX) ++ return -EINVAL; ++ ++ titan_gpio_set_value(chip, gpio, value); ++ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << ++ (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0); ++ ++ return 0; ++} ++ + static struct ar7_gpio_chip ar7_gpio_chip = { + .chip = { + .label = "ar7-gpio", +@@ -87,7 +145,19 @@ static struct ar7_gpio_chip ar7_gpio_chi + } + }; + +-int ar7_gpio_enable(unsigned gpio) ++static struct ar7_gpio_chip titan_gpio_chip = { ++ .chip = { ++ .label = "titan-gpio", ++ .direction_input = titan_gpio_direction_input, ++ .direction_output = titan_gpio_direction_output, ++ .set = titan_gpio_set_value, ++ .get = titan_gpio_get_value, ++ .base = 0, ++ .ngpio = TITAN_GPIO_MAX, ++ } ++}; ++ ++static inline int ar7_gpio_enable_ar7(unsigned gpio) + { + void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; + +@@ -95,9 +165,28 @@ int ar7_gpio_enable(unsigned gpio) + + return 0; + } ++ ++static inline int ar7_gpio_enable_titan(unsigned gpio) ++{ ++ void __iomem *gpio_en0 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0); ++ void __iomem *gpio_en1 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1); ++ ++ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), ++ gpio >> 5 ? gpio_en1 : gpio_en0); ++ ++ return 0; ++} ++ ++int ar7_gpio_enable(unsigned gpio) ++{ ++ return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) : ++ ar7_gpio_enable_ar7(gpio); ++} + EXPORT_SYMBOL(ar7_gpio_enable); + +-int ar7_gpio_disable(unsigned gpio) ++static inline int ar7_gpio_disable_ar7(unsigned gpio) + { + void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; + +@@ -105,27 +194,57 @@ int ar7_gpio_disable(unsigned gpio) + + return 0; + } ++ ++static inline int ar7_gpio_disable_titan(unsigned gpio) ++{ ++ void __iomem *gpio_en0 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0); ++ void __iomem *gpio_en1 = ++ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1); ++ ++ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)), ++ gpio >> 5 ? gpio_en1 : gpio_en0); ++ ++ return 0; ++} ++ ++int ar7_gpio_disable(unsigned gpio) ++{ ++ return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) : ++ ar7_gpio_disable_ar7(gpio); ++} ++ + EXPORT_SYMBOL(ar7_gpio_disable); + + static int __init ar7_gpio_init(void) + { + int ret; + +- ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO, ++ if (!ar7_is_titan()) { ++ ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO, + AR7_REGS_GPIO + 0x10); + +- if (!ar7_gpio_chip.regs) { +- printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n"); +- return -ENOMEM; +- } +- +- ret = gpiochip_add(&ar7_gpio_chip.chip); +- if (ret) { +- printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n"); +- return ret; ++ if (!ar7_gpio_chip.regs) { ++ printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n"); ++ return -ENOMEM; ++ } ++ ++ ret = gpiochip_add(&ar7_gpio_chip.chip); ++ if (ret) { ++ printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n"); ++ return ret; ++ } ++ printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n", ++ ar7_gpio_chip.chip.ngpio); ++ } else { ++ ret = gpiochip_add(&titan_gpio_chip.chip); ++ if (ret) { ++ printk(KERN_ERR "titan-gpio: failed to add gpiochip\n"); ++ return ret; ++ } ++ printk(KERN_INFO "titan-gpio: registered %d GPIOs\n", ++ titan_gpio_chip.chip.ngpio); + } +- printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n", +- ar7_gpio_chip.chip.ngpio); + return ret; + } + arch_initcall(ar7_gpio_init); +--- a/arch/mips/ar7/setup.c ++++ b/arch/mips/ar7/setup.c +@@ -23,6 +23,9 @@ + #include <asm/reboot.h> + #include <asm/mach-ar7/ar7.h> + #include <asm/mach-ar7/prom.h> ++#include <asm/mach-ar7/gpio.h> ++ ++static int titan_variant; + + static void ar7_machine_restart(char *command) + { +@@ -56,6 +59,18 @@ const char *get_system_type(void) + return "TI AR7 (TNETD7200)"; + case AR7_CHIP_7300: + return "TI AR7 (TNETD7300)"; ++ case AR7_CHIP_TITAN: ++ titan_variant = ar7_init_titan_variant(); ++ switch (titan_variant /*(gpio_get_value_titan(1) >> 12) & 0xf*/) { ++ case TITAN_CHIP_1050: ++ return "TI AR7 (TNETV1050)"; ++ case TITAN_CHIP_1055: ++ return "TI AR7 (TNETV1055)"; ++ case TITAN_CHIP_1056: ++ return "TI AR7 (TNETV1056)"; ++ case TITAN_CHIP_1060: ++ return "TI AR7 (TNETV1060)"; ++ } + default: + return "TI AR7 (unknown)"; + } +--- a/arch/mips/include/asm/mach-ar7/ar7.h ++++ b/arch/mips/include/asm/mach-ar7/ar7.h +@@ -50,6 +50,11 @@ + #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) + #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) + ++#define TITAN_REGS_MAC0 (0x08640000) ++#define TITAN_REGS_MAC1 (TITAN_REGS_MAC0 + 0x0800) ++#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) ++#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) ++ + #define AR7_RESET_PERIPHERAL 0x0 + #define AR7_RESET_SOFTWARE 0x4 + #define AR7_RESET_STATUS 0x8 +@@ -59,15 +64,30 @@ + #define AR7_RESET_BIT_MDIO 22 + #define AR7_RESET_BIT_EPHY 26 + ++#define TITAN_RESET_BIT_EPHY1 28 ++ + /* GPIO control registers */ + #define AR7_GPIO_INPUT 0x0 + #define AR7_GPIO_OUTPUT 0x4 + #define AR7_GPIO_DIR 0x8 + #define AR7_GPIO_ENABLE 0xc ++#define TITAN_GPIO_INPUT_0 0x0 ++#define TITAN_GPIO_INPUT_1 0x4 ++#define TITAN_GPIO_OUTPUT_0 0x8 ++#define TITAN_GPIO_OUTPUT_1 0xc ++#define TITAN_GPIO_DIR_0 0x10 ++#define TITAN_GPIO_DIR_1 0x14 ++#define TITAN_GPIO_ENBL_0 0x18 ++#define TITAN_GPIO_ENBL_1 0x1c + + #define AR7_CHIP_7100 0x18 + #define AR7_CHIP_7200 0x2b + #define AR7_CHIP_7300 0x05 ++#define AR7_CHIP_TITAN 0x07 ++#define TITAN_CHIP_1050 0x0f ++#define TITAN_CHIP_1055 0x0e ++#define TITAN_CHIP_1056 0x0d ++#define TITAN_CHIP_1060 0x07 + + /* Interrupts */ + #define AR7_IRQ_UART0 15 +@@ -95,14 +115,22 @@ struct plat_dsl_data { + + extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; + ++static inline int ar7_is_titan(void) ++{ ++ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == ++ AR7_CHIP_TITAN; ++} ++ + static inline u16 ar7_chip_id(void) + { +- return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; ++ return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) ++ KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); + } + + static inline u8 ar7_chip_rev(void) + { +- return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; ++ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : ++ 0x14))) >> 16) & 0xff; + } + + struct clk { +--- a/arch/mips/include/asm/mach-ar7/gpio.h ++++ b/arch/mips/include/asm/mach-ar7/gpio.h +@@ -20,9 +20,13 @@ + #define __AR7_GPIO_H__ + + #include <asm/mach-ar7/ar7.h> ++#ifndef __AR7_TITAN_H__ ++#include <asm/mach-ar7/titan.h> ++#endif + + #define AR7_GPIO_MAX 32 +-#define NR_BUILTIN_GPIO AR7_GPIO_MAX ++#define TITAN_GPIO_MAX 51 ++#define NR_BUILTIN_GPIO TITAN_GPIO_MAX + + #define gpio_to_irq(gpio) -1 + +@@ -35,6 +39,41 @@ + int ar7_gpio_enable(unsigned gpio); + int ar7_gpio_disable(unsigned gpio); + ++static inline int ar7_init_titan_variant(void) ++{ ++ /*UINT32 new_val;*/ ++ unsigned new_val; ++ ++ /* set GPIO 44 - 47 as input */ ++ /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */ ++ /*define titan_gpio_ctrl in titan.h*/ ++ titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN); ++ titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN); ++ titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN); ++ titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN); ++ ++ /* read GPIO to get Titan variant type */ ++ /*fix this*/ ++ titan_sysGpioInValue( &new_val, 1 ); ++ ++ new_val >>= 12; ++ new_val &= 0x0f; ++ ++ switch ( new_val ) ++ { ++ case TITAN_CHIP_1050: ++ case TITAN_CHIP_1055: ++ case TITAN_CHIP_1056: ++ case TITAN_CHIP_1060: ++ return new_val; ++ ++ default: ++ break; ++ } ++ /* In case we get an invalid value, return the default Titan chip */ ++ return TITAN_CHIP_1050; ++} ++ + #include <asm-generic/gpio.h> + + #endif +--- /dev/null ++++ b/arch/mips/include/asm/mach-ar7/titan.h +@@ -0,0 +1,176 @@ ++/* ++ * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#ifndef __AR7_TITAN_H__ ++#define __AR7_TITAN_H__ ++ ++#include <asm/mach-ar7/gpio.h> ++ ++typedef enum TITAN_GPIO_PIN_MODE_tag ++{ ++ FUNCTIONAL_PIN = 0, ++ GPIO_PIN = 1 ++} TITAN_GPIO_PIN_MODE_T; ++ ++typedef enum TITAN_GPIO_PIN_DIRECTION_tag ++{ ++ GPIO_OUTPUT_PIN = 0, ++ GPIO_INPUT_PIN = 1 ++} TITAN_GPIO_PIN_DIRECTION_T; ++ ++/********************************************************************** ++ * GPIO Control ++ **********************************************************************/ ++ ++typedef struct ++{ ++ int pinSelReg; ++ int shift; ++ int func; ++ ++} GPIO_CFG; ++ ++static GPIO_CFG gptable[]= { ++ /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */ ++ {4,24,1}, ++ {4,26,1}, ++ {4,28,1}, ++ {4,30,1}, ++ {5,6,1}, ++ {5,8,1}, ++ {5,10,1}, ++ {5,12,1}, ++ {7,14,3}, ++ {7,16,3}, ++ {7,18,3}, ++ {7,20,3}, ++ {7,22,3}, ++ {7,26,3}, ++ {7,28,3}, ++ {7,30,3}, ++ {8,0,3}, ++ {8,2,3}, ++ {8,4,3}, ++ {8,10,3}, ++ {8,14,3}, ++ {8,16,3}, ++ {8,18,3}, ++ {8,20,3}, ++ {9,8,3}, ++ {9,10,3}, ++ {9,12,3}, ++ {9,14,3}, ++ {9,18,3}, ++ {9,20,3}, ++ {9,24,3}, ++ {9,26,3}, ++ {9,28,3}, ++ {9,30,3}, ++ {10,0,3}, ++ {10,2,3}, ++ {10,8,3}, ++ {10,10,3}, ++ {10,12,3}, ++ {10,14,3}, ++ {13,12,3}, ++ {13,14,3}, ++ {13,16,3}, ++ {13,18,3}, ++ {13,24,3}, ++ {13,26,3}, ++ {13,28,3}, ++ {13,30,3}, ++ {14,2,3}, ++ {14,6,3}, ++ {14,8,3}, ++ {14,12,3} ++}; ++ ++typedef struct ++{ ++ volatile unsigned int reg[21]; ++} ++PIN_SEL_REG_ARRAY_T; ++ ++typedef struct ++{ ++ unsigned int data_in [2]; ++ unsigned int data_out[2]; ++ unsigned int dir[2]; ++ unsigned int enable[2]; ++ ++} TITAN_GPIO_CONTROL_T; ++ ++#define AVALANCHE_PIN_SEL_BASE 0xA861160C /*replace with KSEG1ADDR()*/ ++ ++static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode, ++ TITAN_GPIO_PIN_DIRECTION_T pin_direction) ++{ ++ int reg_index = 0; ++ int mux_status; ++ GPIO_CFG gpio_cfg; ++ volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE; ++ volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0); ++ ++ if (gpio_pin > 51 ) ++ return(-1); ++ ++ gpio_cfg = gptable[gpio_pin]; ++ mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3; ++ if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/))) ++ { ++ return(-1); /* Pin have been configured for non GPIO funcs. */ ++ } ++ ++ /* Set the pin to be used as GPIO. */ ++ pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift); ++ ++ /* Check whether gpio refers to the first GPIO reg or second. */ ++ if(gpio_pin > 31) ++ { ++ reg_index = 1; ++ gpio_pin -= 32; ++ } ++ ++ if(pin_mode) ++ gpio_cntl->enable[reg_index] |= (1 << gpio_pin); /* Enable */ ++ else ++ gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin); ++ ++ if(pin_direction) ++ gpio_cntl->dir[reg_index] |= (1 << gpio_pin); /* Input */ ++ else ++ gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin); ++ ++ return(0); ++ ++}/* end of function titan_gpio_ctrl */ ++ ++static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index) ++{ ++ volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0); ++ ++ if(reg_index > 1) ++ return (-1); ++ ++ *in_val = gpio_cntl->data_in[reg_index]; ++ ++ return (0); ++} ++ ++ ++#endif diff --git a/target/linux/ar7/patches-2.6.35/940-cpmac-titan.patch b/target/linux/ar7/patches-2.6.35/940-cpmac-titan.patch new file mode 100644 index 000000000..ec4465528 --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/940-cpmac-titan.patch @@ -0,0 +1,108 @@ +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -769,22 +769,31 @@ static int __init ar7_register_devices(v + } + + if (ar7_has_high_cpmac()) { +- res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status); ++ fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_high_titan.id : cpmac_high.id, ++ &fixed_phy_status); + if (!res) { +- cpmac_get_mac(1, cpmac_high_data.dev_addr); +- +- res = platform_device_register(&cpmac_high); ++ cpmac_get_mac(1, ar7_is_titan() ? cpmac_high_data_titan.dev_addr : ++ cpmac_high_data.dev_addr); ++ res = platform_device_register(ar7_is_titan() ? &cpmac_high_titan : ++ &cpmac_high); + if (res) + pr_warning("unable to register cpmac-high: %d\n", res); + } else + pr_warning("unable to add cpmac-high phy: %d\n", res); +- } else +- cpmac_low_data.phy_mask = 0xffffffff; ++ } else { ++ if (ar7_is_titan()) ++ cpmac_low_data_titan.phy_mask = 0xffffffff; ++ else ++ cpmac_low_data.phy_mask = 0xffffffff; ++ } + +- res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); ++ res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_low_titan.id : cpmac_low.id, ++ &fixed_phy_status); + if (!res) { +- cpmac_get_mac(0, cpmac_low_data.dev_addr); +- res = platform_device_register(&cpmac_low); ++ cpmac_get_mac(0, ar7_is_titan() ? cpmac_low_data_titan.dev_addr : ++ cpmac_low_data.dev_addr); ++ res = platform_device_register(ar7_is_titan() ? &cpmac_low_titan : ++ &cpmac_low); + if (res) + pr_warning("unable to register cpmac-low: %d\n", res); + } else +--- a/drivers/net/cpmac.c ++++ b/drivers/net/cpmac.c +@@ -1158,6 +1158,8 @@ static int __devinit cpmac_probe(struct + goto fail; + } + ++ ar7_device_reset(pdata->reset_bit); ++ + dev->irq = platform_get_irq_byname(pdev, "irq"); + + dev->netdev_ops = &cpmac_netdev_ops; +@@ -1234,7 +1236,7 @@ int __devinit cpmac_init(void) + cpmac_mii->reset = cpmac_mdio_reset; + cpmac_mii->irq = mii_irqs; + +- cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); ++ cpmac_mii->priv = ioremap(ar7_is_titan() ? TITAN_REGS_MDIO : AR7_REGS_MDIO, 256); + + if (!cpmac_mii->priv) { + printk(KERN_ERR "Can't ioremap mdio registers\n"); +@@ -1245,10 +1247,17 @@ int __devinit cpmac_init(void) + #warning FIXME: unhardcode gpio&reset bits + ar7_gpio_disable(26); + ar7_gpio_disable(27); +- ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); +- ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); ++ ++ if (!ar7_is_titan()) { ++ ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); ++ ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); ++ } + ar7_device_reset(AR7_RESET_BIT_EPHY); + ++ if (ar7_is_titan()) { ++ ar7_device_reset(TITAN_RESET_BIT_EPHY1); ++ } ++ + cpmac_mii->reset(cpmac_mii); + + for (i = 0; i < 300; i++) +@@ -1263,7 +1272,8 @@ int __devinit cpmac_init(void) + mask = 0; + } + +- cpmac_mii->phy_mask = ~(mask | 0x80000000); ++ cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000): ++ ~(mask | 0x80000000); + snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1"); + + res = mdiobus_register(cpmac_mii); +--- a/arch/mips/include/asm/mach-ar7/ar7.h ++++ b/arch/mips/include/asm/mach-ar7/ar7.h +@@ -50,8 +50,10 @@ + #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) + #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) + +-#define TITAN_REGS_MAC0 (0x08640000) +-#define TITAN_REGS_MAC1 (TITAN_REGS_MAC0 + 0x0800) ++#define TITAN_REGS_ESWITCH_BASE (0x08640000) ++#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE + 0) ++#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) ++#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) + #define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) + #define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) + diff --git a/target/linux/ar7/patches-2.6.35/970-remove_fixed_phy.patch b/target/linux/ar7/patches-2.6.35/970-remove_fixed_phy.patch new file mode 100644 index 000000000..c8a00dfbc --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/970-remove_fixed_phy.patch @@ -0,0 +1,78 @@ +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -33,7 +33,6 @@ + #include <linux/string.h> + #include <linux/etherdevice.h> + #include <linux/phy.h> +-#include <linux/phy_fixed.h> + #include <linux/gpio.h> + #include <linux/clk.h> + +@@ -370,12 +369,6 @@ static struct resource cpmac_high_res_ti + }, + }; + +-static struct fixed_phy_status fixed_phy_status __initdata = { +- .link = 1, +- .speed = 100, +- .duplex = 1, +-}; +- + static struct plat_cpmac_data cpmac_low_data = { + .reset_bit = 17, + .power_bit = 20, +@@ -769,16 +762,13 @@ static int __init ar7_register_devices(v + } + + if (ar7_has_high_cpmac()) { +- fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_high_titan.id : cpmac_high.id, +- &fixed_phy_status); +- if (!res) { +- cpmac_get_mac(1, ar7_is_titan() ? cpmac_high_data_titan.dev_addr : ++ cpmac_get_mac(1, ar7_is_titan() ? cpmac_high_data_titan.dev_addr : + cpmac_high_data.dev_addr); +- res = platform_device_register(ar7_is_titan() ? &cpmac_high_titan : ++ res = platform_device_register(ar7_is_titan() ? &cpmac_high_titan : + &cpmac_high); +- if (res) +- pr_warning("unable to register cpmac-high: %d\n", res); +- } else ++ if (res) ++ pr_warning("unable to register cpmac-high: %d\n", res); ++ else + pr_warning("unable to add cpmac-high phy: %d\n", res); + } else { + if (ar7_is_titan()) +@@ -787,16 +777,13 @@ static int __init ar7_register_devices(v + cpmac_low_data.phy_mask = 0xffffffff; + } + +- res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_low_titan.id : cpmac_low.id, +- &fixed_phy_status); +- if (!res) { +- cpmac_get_mac(0, ar7_is_titan() ? cpmac_low_data_titan.dev_addr : ++ cpmac_get_mac(0, ar7_is_titan() ? cpmac_low_data_titan.dev_addr : + cpmac_low_data.dev_addr); +- res = platform_device_register(ar7_is_titan() ? &cpmac_low_titan : ++ res = platform_device_register(ar7_is_titan() ? &cpmac_low_titan : + &cpmac_low); +- if (res) +- pr_warning("unable to register cpmac-low: %d\n", res); +- } else ++ if (res) ++ pr_warning("unable to register cpmac-low: %d\n", res); ++ else + pr_warning("unable to add cpmac-low phy: %d\n", res); + + detect_leds(); +--- a/drivers/net/cpmac.c ++++ b/drivers/net/cpmac.c +@@ -1273,7 +1273,7 @@ int __devinit cpmac_init(void) + } + + cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000): +- ~(mask | 0x80000000); ++ ~(mask | 0x80000001); + snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1"); + + res = mdiobus_register(cpmac_mii); diff --git a/target/linux/ar7/patches-2.6.35/971-cpmac_cleanup.patch b/target/linux/ar7/patches-2.6.35/971-cpmac_cleanup.patch new file mode 100644 index 000000000..99e8fbe8d --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/971-cpmac_cleanup.patch @@ -0,0 +1,69 @@ +--- a/drivers/net/cpmac.c ++++ b/drivers/net/cpmac.c +@@ -34,7 +34,6 @@ + #include <linux/skbuff.h> + #include <linux/mii.h> + #include <linux/phy.h> +-#include <linux/phy_fixed.h> + #include <linux/platform_device.h> + #include <linux/dma-mapping.h> + #include <linux/clk.h> +@@ -1108,8 +1107,6 @@ static const struct net_device_ops cpmac + .ndo_set_mac_address = eth_mac_addr, + }; + +-static int external_switch; +- + static int __devinit cpmac_probe(struct platform_device *pdev) + { + int rc, phy_id; +@@ -1121,24 +1118,18 @@ static int __devinit cpmac_probe(struct + + pdata = pdev->dev.platform_data; + +- if (external_switch || dumb_switch) { +- strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */ +- phy_id = pdev->id; +- } else { +- for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { +- if (!(pdata->phy_mask & (1 << phy_id))) +- continue; +- if (!cpmac_mii->phy_map[phy_id]) +- continue; +- strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE); +- break; +- } ++ for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { ++ if (!(pdata->phy_mask & (1 << phy_id))) ++ continue; ++ if (!cpmac_mii->phy_map[phy_id]) ++ continue; ++ strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE); ++ break; + } + + if (phy_id == PHY_MAX_ADDR) { +- dev_err(&pdev->dev, "no PHY present, falling back to switch on MDIO bus 0\n"); +- strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */ +- phy_id = pdev->id; ++ dev_err(&pdev->dev, "no PHY present\n"); ++ return -ENODEV; + } + + dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES); +@@ -1266,14 +1257,8 @@ int __devinit cpmac_init(void) + else + msleep(10); + +- mask &= 0x7fffffff; +- if (mask & (mask - 1)) { +- external_switch = 1; +- mask = 0; +- } +- + cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000): +- ~(mask | 0x80000001); ++ ~(mask | 0x80000000); + snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1"); + + res = mdiobus_register(cpmac_mii); diff --git a/target/linux/ar7/patches-2.6.35/972-cpmac_multi_probe.patch b/target/linux/ar7/patches-2.6.35/972-cpmac_multi_probe.patch new file mode 100644 index 000000000..7ee604a76 --- /dev/null +++ b/target/linux/ar7/patches-2.6.35/972-cpmac_multi_probe.patch @@ -0,0 +1,65 @@ +--- a/drivers/net/cpmac.c ++++ b/drivers/net/cpmac.c +@@ -34,6 +34,7 @@ + #include <linux/skbuff.h> + #include <linux/mii.h> + #include <linux/phy.h> ++#include <linux/phy_fixed.h> + #include <linux/platform_device.h> + #include <linux/dma-mapping.h> + #include <linux/clk.h> +@@ -219,6 +220,12 @@ static void cpmac_hw_stop(struct net_dev + static int cpmac_stop(struct net_device *dev); + static int cpmac_open(struct net_device *dev); + ++static struct fixed_phy_status fixed_phy_status = { ++ .link = 1, ++ .speed = 100, ++ .duplex = 1, ++}; ++ + static void cpmac_dump_regs(struct net_device *dev) + { + int i; +@@ -1127,11 +1134,38 @@ static int __devinit cpmac_probe(struct + break; + } + +- if (phy_id == PHY_MAX_ADDR) { +- dev_err(&pdev->dev, "no PHY present\n"); +- return -ENODEV; ++ if (phy_id < PHY_MAX_ADDR) ++ goto dev_alloc; ++ ++ dev_info(&pdev->dev, "trying external MII\n"); ++ /* Now disable EPHY and enable MII */ ++ ar7_device_disable(AR7_RESET_BIT_EPHY); ++ *(unsigned long*) ioremap(0x08611A08, 4) |= 0x00000001; ++ ++ for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { ++ if (!(pdata->phy_mask & (1 << phy_id))) ++ continue; ++ if (!cpmac_mii->phy_map[phy_id]) ++ continue; ++ strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE); ++ break; + } + ++ if (phy_id < PHY_MAX_ADDR) ++ goto dev_alloc; ++ ++ /* This still does not work, so now we register a fixed phy */ ++ dev_info(&pdev->dev, "using fixed PHY\n"); ++ rc = fixed_phy_add(PHY_POLL, pdev->id, &fixed_phy_status); ++ if (rc && rc != -ENODEV) { ++ dev_err(&pdev->dev, "unable to register fixed PHY\n"); ++ return rc; ++ } ++ ++ strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */ ++ phy_id = pdev->id; ++ ++dev_alloc: + dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES); + + if (!dev) { |