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path: root/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c128
1 files changed, 118 insertions, 10 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index d2d0ee87f..d7f3595b8 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -181,6 +181,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
if (ath79_soc == ATH79_SOC_AR9341 ||
ath79_soc == ATH79_SOC_AR9342 ||
ath79_soc == ATH79_SOC_AR9344 ||
+ ath79_soc == ATH79_SOC_QCA9556 ||
ath79_soc == ATH79_SOC_QCA9558)
max_id = 1;
else
@@ -202,6 +203,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
if (id == 0) {
mdio_dev = &ath79_mdio0_device;
@@ -250,12 +252,17 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
}
mdio_data->is_ar934x = 1;
break;
+
case ATH79_SOC_QCA9558:
if (id == 1)
mdio_data->builtin_switch = 1;
mdio_data->is_ar934x = 1;
break;
+ case ATH79_SOC_QCA9556:
+ mdio_data->is_ar934x = 1;
+ break;
+
default:
break;
}
@@ -355,6 +362,26 @@ static void ar934x_set_speed_ge0(int speed)
iounmap(base);
}
+static void qca955x_set_speed_xmii(int speed)
+{
+ void __iomem *base;
+ u32 val = ath79_get_eth_pll(0, speed);
+
+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+ __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
+ iounmap(base);
+}
+
+static void qca955x_set_speed_sgmii(int speed)
+{
+ void __iomem *base;
+ u32 val = ath79_get_eth_pll(1, speed);
+
+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+ __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
+ iounmap(base);
+}
+
static void ath79_set_speed_dummy(int speed)
{
}
@@ -412,8 +439,8 @@ static struct resource ath79_eth0_resources[] = {
}, {
.name = "mac_irq",
.flags = IORESOURCE_IRQ,
- .start = ATH79_CPU_IRQ_GE0,
- .end = ATH79_CPU_IRQ_GE0,
+ .start = ATH79_CPU_IRQ(4),
+ .end = ATH79_CPU_IRQ(4),
},
};
@@ -440,8 +467,8 @@ static struct resource ath79_eth1_resources[] = {
}, {
.name = "mac_irq",
.flags = IORESOURCE_IRQ,
- .start = ATH79_CPU_IRQ_GE1,
- .end = ATH79_CPU_IRQ_GE1,
+ .start = ATH79_CPU_IRQ(5),
+ .end = ATH79_CPU_IRQ(5),
},
};
@@ -540,6 +567,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
pll_10 = AR934X_PLL_VAL_10;
pll_100 = AR934X_PLL_VAL_100;
@@ -605,7 +633,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
- case ATH79_SOC_QCA9558:
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
@@ -617,6 +644,18 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
}
break;
+ case ATH79_SOC_QCA9556:
+ case ATH79_SOC_QCA9558:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_SGMII:
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+
default:
BUG();
}
@@ -654,7 +693,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
- case ATH79_SOC_QCA9558:
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
@@ -664,6 +702,18 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
}
break;
+ case ATH79_SOC_QCA9556:
+ case ATH79_SOC_QCA9558:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_SGMII:
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+
default:
BUG();
}
@@ -691,6 +741,30 @@ void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
iounmap(base);
}
+void __init ath79_setup_ar934x_eth_cfg(u32 mask)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
+ AR934X_ETH_CFG_MII_GMAC0 |
+ AR934X_ETH_CFG_GMII_GMAC0 |
+ AR934X_ETH_CFG_SW_ONLY_MODE |
+ AR934X_ETH_CFG_SW_PHY_SWAP);
+
+ t |= mask;
+
+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+ /* flush write */
+ __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
static int ath79_eth_instance __initdata;
void __init ath79_register_eth(unsigned int id)
{
@@ -861,7 +935,6 @@ void __init ath79_register_eth(unsigned int id)
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
- case ATH79_SOC_QCA9558:
if (id == 0) {
pdata->reset_bit = AR934X_RESET_GE0_MAC |
AR934X_RESET_GE0_MDIO;
@@ -890,6 +963,30 @@ void __init ath79_register_eth(unsigned int id)
pdata->fifo_cfg3 = 0x01f00140;
break;
+ case ATH79_SOC_QCA9556:
+ case ATH79_SOC_QCA9558:
+ if (id == 0) {
+ pdata->reset_bit = QCA955X_RESET_GE0_MAC |
+ QCA955X_RESET_GE0_MDIO;
+ pdata->set_speed = qca955x_set_speed_xmii;
+ } else {
+ pdata->reset_bit = QCA955X_RESET_GE1_MAC |
+ QCA955X_RESET_GE1_MDIO;
+ pdata->set_speed = qca955x_set_speed_sgmii;
+ }
+
+ pdata->ddr_flush = ath79_ddr_no_flush;
+ pdata->has_gbit = 1;
+ pdata->is_ar724x = 1;
+
+ if (!pdata->fifo_cfg1)
+ pdata->fifo_cfg1 = 0x0010ffff;
+ if (!pdata->fifo_cfg2)
+ pdata->fifo_cfg2 = 0x015500aa;
+ if (!pdata->fifo_cfg3)
+ pdata->fifo_cfg3 = 0x01f00140;
+ break;
+
default:
BUG();
}
@@ -897,6 +994,7 @@ void __init ath79_register_eth(unsigned int id)
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_SGMII:
if (!pdata->has_gbit) {
printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
id);
@@ -919,7 +1017,6 @@ void __init ath79_register_eth(unsigned int id)
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
- case ATH79_SOC_QCA9558:
if (id == 0)
pdata->mii_bus_dev = &ath79_mdio0_device.dev;
else
@@ -932,6 +1029,11 @@ void __init ath79_register_eth(unsigned int id)
pdata->mii_bus_dev = &ath79_mdio1_device.dev;
break;
+ case ATH79_SOC_QCA9556:
+ case ATH79_SOC_QCA9558:
+ /* don't assign any MDIO device by default */
+ break;
+
default:
pdata->mii_bus_dev = &ath79_mdio0_device.dev;
break;
@@ -992,7 +1094,10 @@ void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
{
int t;
- if (!is_valid_ether_addr(src)) {
+ if (!dst)
+ return;
+
+ if (!src || !is_valid_ether_addr(src)) {
memset(dst, '\0', ETH_ALEN);
return;
}
@@ -1012,7 +1117,10 @@ void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
{
int i;
- if (!is_valid_ether_addr(src)) {
+ if (!dst)
+ return;
+
+ if (!src || !is_valid_ether_addr(src)) {
memset(dst, '\0', ETH_ALEN);
return;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-23 16:15:30 +0000